View NCN6004A06_1287682.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

NCN6004A Dual SAM/SIM Interface Integrated Circuit
The NCN6004A is an interface IC dedicated for Secured Access Module reader/writer applications. It allows the management of two external ISO/EMV cards thanks to a simple and flexible microcontroller interface. Several NCN6004A interfaces can share a single data bus, assuming the external MPU provides the right Chip Select signals to identify each IC connected on the bus. A built in accurate protection system guarantees timely and controlled shutdown in the case of external error conditions. On top of that, the NCN6004A can independently handle the power supply, in the range 2.7 V to 5.0 V input voltage, provided to each external Smart Card. The interface monitors the current flowing into each Smart Card, a flag being set in the case of overload.
Features http://onsemi.com
1
* Separated, Built-in DC/DC Converters Supply VCC Power to * * * * * * * * * * * * * * * * * *
External Cards 100% Compatible with ISO 7816-3, EMV and GIE-CB Standards Fully GSM Compliant Individually Programmable ISO/EMV Clock Generator Built-in Programmable CRD_CLK Stop Function Handles Run or High/Low State Programmable CRD_CLK Slopes to Cope with Wide Operating Frequency Range Programmable Independent VCC Supply for Each Smart Card Support up to 65 mA VCC Supply to Each ISO/EMV Card Multiple NCN6004A Parallel Operation on a Shared Bus 8 kV/Human Model ESD Protection on Each Interface Pin Provides C4/C8 Channels Provides 1.8 V, 3.0 V or 5.0 V Card Supply Voltages Pb-Free Package is Available*
TQFP48 CASE 932F PLASTIC
MARKING DIAGRAM
NCN6004A AWLYYWWG
48 1
Typical Applications
Set Top Box Decoder ATM Multi Systems, POS, Handheld Terminals Internet E-commerce PC Interface Multiple Self Serve Automatic Machines Wireless Phone Payment Interface Automotive Operating Time Controller
A WL YY WW G
= Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package
ORDERING INFORMATION
Device NCN6004AFTBR2 NCN6004AFTBR2G Package TQFP48 TQFP48 (Pb-Free) Shipping 2000/Tape & Reel 2000/Tape & Reel
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2006
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Publication Order Number: NCN6004A/D
1
March, 2006 - Rev. 3
NCN6004A
CRD_DET_B MUX_MODE ANLG_GND ANLG_GND ANLG_VCC CRD_C8_B CRD_C4_B CRD_RST_B 38 CRD_IO_B 37 36 PWR_GND 35 L2b 34 L1b 33 PWR_VCC_B 32 CRD_VCC_B 31 CRD_CLK_B 30 CRD_CLK_A 29 CRD_VCC_A 28 PWR_VCC_A 27 L1a 26 L2a 25 PWR_GND 13 CLOCK_IN_A 14 ANLG_GND 15 CLOCK_IN_B 16 C8_B 17 C4_B 18 RESET_B 19 I/O_B 20 CRD_DET_A 21 CRD_C8_A 22 CRD_C4_A 23 CRD_RST_A 24 CRD_IO_A
48 A0 A1 A2 A3 CARD_SEL PGM CS PWR_ON I/O_A 1 2 3 4 5 6 7 8 9
47 46
45
EN_RPU
STATUS
INT
44
43
42
41
40
39
RESET_A 10 C4_A 11 C8_A 12
Figure 1. Pin Diagram
L2 J1 17 C3 41 10 mF 32 38 31 39 40 37 33 28 36 25 20 29 23 30 22 21 24 C1 10 mF VCC J2 17 C2 10 mF GND 1V CC 2 3 4 RST CLK C4 GND VPP I/O C8 5 6 7 8 GND SMARTCARD # B DET DET 18 GND 1V CC 2 RST 3 CLK 4 C4 GND VPP I/O C8 5 6 7 8 GND SMARTCARD # A DET DET 18
L1
CHIP SELECT MPU BUS
MICRO CONTROLLER
VCC IRQ GND
1 2 3 4 5 6 7 8 44 45 46 47 9 10 11 12 13
27 22 mH 26 34 22 mH 35 L2a L1a L1b L2b A0 CRD_DET_B A1 CRD_VCC_B A2 A3 CRD_RST_B CARD_SEL CRD_CLK_B PGM CRD_C4_B CS PWR_ON CRD_C8_B MUX_MODE EN_RPU CRD_IO_B STATUS PWR_VCC_B INT I/O_A RESET_A NCN6004A PWR_GND C4_A C8_A PWR_GND CLK_IN_A ANLG_GND CLK_IN_B C8_B C4_B RESET_B I/O_B CRD_DET_A CRD_VCC_A CRD_RST_A CRD_CLK_A CRD_C4_A CRD_C8_A CRD_IO_A ANLG_GND ANLG_VCC ANLG_GND PWR_VCC_A
DATA PORT#B DATA PORT#A
GND
GND
14 15 16 17 18 19
42 VCC C4
43 48 100 nF GND
Figure 2. Typical Application http://onsemi.com
2
NCN6004A
ANLG_VCC AGND
42 43 GND
INPUT VOLTAGE MONITOR 28 CARD#A DC/DC CONVERTER 27 PWR_VCCA L2a
INT STATUS
47 46
50 k 50 k 100 k VCC
VCC VCC
DET#A
INTERRUPT BLOCK
DET#B
26
L1a
29 CRD_VCCA 25 PWR_GND GND
CS PWR_ON A0 A1 A2 A3 CARD_SEL PGM CLK_INA
7 8 1 2 3 4 5 6 CLOCK#A DIVIDER CLK#A CNTL DIGITAL BLOCK
CARD#A SEQUENCER
CARD #A PINS DRIVERS
C8A C4A CLK_A RESET_A I/O#A
21 CRD_C8A 22 CRD_C4A 30 CRD_CLKA 24 CRD_IOA 23 CRD_RSTA
IO_A RST_A C4A C8A CONTROL
CLK#A DET#A
13
CARD#A DETECTION
20
CRD_DETA
CLK_INB
15
CLOCK#B DIVIDER CLK#B 26 k
DET#B
CARD#B DETECTION
41
CRD_DETB
CARD#B SEQUENCER
C8B C4B CLK_B RESET_A I/O#B
40 CRD_C8B CARD#B PINS DRIVERS 39 CRD_C4B 38 CRD_RSTB 37 CRD_IOB 31 CRD_CLKB
I/O_A RESET_A C4A
9 10 11
IO_B 100 k 100 k 100 k 26 k 100 k 100 k 100 k CNTL ANALOG & DIGITAL MULTIPLEX RST_B C4B C8B
C8A 12 I/O_B RESET_B C4B C8B EN_RPU MUX_MODE 19 18 17 16 45
IO_A RST_A C4A C8A
CLK#B
CARD#B DC/DC CONVERTER
32 CRD_VCCB 36 PWR_GND GND 34 L2b
IO_B RST_B C4B C8B NOTE:
35
L1b
33 PWR_VCCB
44
An internal active pull down device forces all the smart card pins to zero when the chip is deactivated.
Figure 3. Block Diagram
http://onsemi.com
3
NCN6004A
PIN DESCRIPTION
Pin 1 Symbol A0 Type INPUT Description This pin is combined with CS, A1, A2, A3, CARD_SEL and PGM to program the chip mode of operation, the CRD_VCC voltage value, and to read the data provided by the internal STATUS register (Table 1). This pin is combined with CS, A0, A2, A3, CARD_SEL and PGM to program the chip mode of operation, the CRD_VCC voltage value, and to read the data provided by the internal STATUS register (Table 1). This pin is combined with CS, A0, A1, A3, CARD_SEL and PGM to program the chip mode of operation, the CRD_VCC voltage value, and to read the data provided by the internal STATUS register (Table 1). This pin is combined with CS, A0, A1, A2, CARD_SEL and PGM to program the chip mode of operation, the CRD_VCC voltage value, and to read the data provided by the internal STATUS register (Table 1). This pin provides logic identification of the Card #A/Card #B external smart card. The logic signal is set up by the external microcontroller. CARD_SEL = High selection of the Smart Card A connected to pins 20, 21, 22, 23, 24, 29 and 30 (respectively CRD_DET_A, CRD_C8_A, CRD_C4_A, CRD_RST_A, CRD_IO_A, CRD_VCC_A and CRD_CLK_A). CARD_SEL = Low selection of the Smart Card B connected to pins 41, 39, 40, 31, 38, 37, and 32 (respectively CRD_DET_B, CRD_C4_B, CRD_C8_B, CRD_CLK_B, CRD_RST_B, CRD_IO_B, and CRD_VCC_B). This pin is combined with CS, A0, A1, A2, A3, and CARD_SEL to program the chip mode of operation and to read the data provided by the internal STATUS register (Figure 4 and Table 1). PGM = H the NCN6004A is under normal operation and all the data with the external card can be exchanged using any of the Smart Card A or Smart Card B Lines PGM = Low the NCN6004A runs the programming mode and related parameters can be re programmed according to a given need. In this case, the related card side logic signals are latched in their previous states and no transaction can occurs. The programmed states are latched upon the PGM rising slope (Figure 4).
2
A1
INPUT
3
A2
INPUT
4
A3
INPUT
5
CARD_SEL
INPUT
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA AAAAAAAAAAAAAAAAAAAAAA A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAA
6 PGM DIGITAL INPUT 7 CS DIGITAL INPUT This pin provides the Chip Select Function for the NCN6004A device. CS = High Pins A0, A1, A2, A3, CARD_SEL, PGM, PWR_ON, RESET_A, RESET_B, C4_A, C4_B, C8_A, C8_B, I/O_A and I/O_B are disabled, the pre activated CRD_VCC maintains it's currently programmed value. CS = Low Pins A0, A1, A2, A3, CARD_SEL, PGM, PWR_ON, RESET_A, RESET_B, C4_A, C4_B, C8_A, C8_B, I/O_A and I/O_B are activated, all the functions being available.An internal pull up resistor, connected to VCC, provides a logic bias when the external mP is in the high impedance state. 8 PWR_ON DIGITAL INPUT This pin activates or deactivates the DC/DC converter selected by CARD_SEL upon positive/negative going transient. PWR_ON = Positive going High DC/DC Activated PWR_ON = Negative going L DC/DC switched Off, no power is applied to the associated output CRD_VCC pin. Since uncontrolled action could take place during the rise voltage of the related CRD_VCC_x output, care must be observed to avoid a PWR_ON negative going transient during this period of time. To avoid any logical latch up, using a minimum 1.0 ms delay is recommended prior to power down the related DC/DC converter following a power up command (Figure 12). 9 I/O_A INPUT/OUTPUT This pin carries the data transmission between an external microcontroller and the external smart card #A. A built-in bi-directional level translator adapts the signal flowing between the card and the MCU. The level translator is enabled when CS = Low. Since a dedicated line is used to communicate the data between the MPU and the smart card, the user can activate the two channels simultaneously, assuming the mP provides a pair of I/O lines. When MUX_MODE = High, this pin provides an access to either card A or B I/O by means of CARD_SEL selection bit. On the other hand, the internal pull up resistor is automatically disconnected when MUX_MODE = High, avoiding a current overload on the I/O line, regardless of the EN_RPU logic level. This pull up resistor is under the EN_RPU control when MUX_MODE = Low.
http://onsemi.com
4
NCN6004A
PIN DESCRIPTION (continued)
Pin 10 Symbol RESET_A Type INPUT Description The signal present on this pin is translated to the RST pin of the external smart card #A. The CS signal must be Low to validate the RESET function, regardless of the selected card. Assuming the mP provides two independent lines to control the RESET pins, the NCN6004A can control two cards simultaneously. When MUX_MODE = High, this pin provides an access to either card A or B Reset by means of CARD_SEL selection bit. The associated pull up resistor is either connected to VCC (EN_RPU = H) or disconnected when EN_RPU = Low. This pin controls the card #A C4 contact The signal can be either de-multiplexed, at MPU level, or is multiplexed with C4_B, depending upon the MUX_MODE logic state. When MUX_MODE = High, this pin provides an access to either card A or B C4 channel by means of CARD_SEL selection bit. The associated pull up resistor is either connected to VCC (EN_RPU = H) or disconnected when EN_RPU = Low. This pin controls the card #A C8 contact. The signal can be either de-multiplexed, at MPU level, or is multiplexed with C8_B, depending upon the MUX_MODE logic state. When MUX_MODE = High, this pin provides an access to either card A or B C8 channel by means of CARD_SEL selection bit. The associated pull up resistor is either connected to VCC (EN_RPU = H) or disconnected when EN_RPU = Low. The signal present on this pin comes from either the MCU master clock, or from any signal fulfilling the logic level and frequency specifications. This signal is fed to the internal clock selection circuit prior to be connected to the external smart card #A. Each of the external card can have different division ratio, depending upon the state of the CRD_SEL pin and associated programming bits. The built-in circuit can be programmed to 1/1, 1/2, 1/4 or 1/8 frequency division ratio. This input is valid and routed to either CRD_CLK_A _DIVIDER or CRD_CLK_B_DIVIDER regardless of the MUX_MODE state, depending upon the CLK_D_A/CRD_D_B and CARD_SEL programmed states (Table 1). Although this input supports the signal coming from a crystal oscillator, care must be observed to avoid digital levels outside the specified VIH/VIL range. Similarly, the input clock signal shall have rise and fall times compatible with the operating frequency. This pin is the ground reference for both analog and digital signals and must be connected to the system Ground. Care must be observed to provide a copper PCB layout designed to avoid small signals and power transients sharing the same track. Good high frequency techniques are strongly recommended. The signal present on this pin comes from either the MCU master clock, or from any signal fulfilling the logic level and frequency specifications. This signal is fed to the internal clock selection circuit prior to be connected to the external smart card #B. Each of the external card can have different division ratio, depending upon the state of the CRD_SEL pin and associated programming bits. The built-in circuit can be programmed to 1/1, 1/2, 1/4, or 1/8 frequency division ratio. This input is valid and routed to either CRD_CLK_B_DIVIDER or CRD_CLK_A_DIVIDER regardless of the MUX_MODE state, depending upon the CRD_D_B/CRD_D_A and CARD_SEL programmed states (Table 1). Although this input supports the signal coming from a crystal oscillator, care must be observed to avoid digital levels outside the specified VIH/VIL range. Similarly, the input clock signal shall have rise and fall times compatible with the operating frequency. This pin controls the card #B C8 contact. The signal can be either de -multiplexed, at MPU level, or is multiplexed with C8_A, depending upon the MUX_MODE logic state. When MUX_MODE = High, this pin is internally disable, a pull up resistor is connected to VCC (regardless of the logic state of EN_RPU is), and the access to card B takes place by C8_A associated with CARD_SEL selection bit. The associated pull up resistor is either connected to VCC (EN_RPU = H) or disconnected when EN_RPU = Low. This pin controls the card #B C4 contact. The signal can be either de -multiplexed, at MPU level, or is multiplexed with C8_A, depending upon the MUX_MODE logic state. When MUX_MODE = High, this pin is internally disable, a pull up resistor is connected to VCC, (regardless of the logic state of EN_RPU), and the access to card B takes place by C4_A associated with CARD_SEL selection bit. The associated pull up resistor is either connected to VCC (EN_RPU = H) or disconnected when EN_RPU = Low.
11
C4_A
INPUT
12
C8_A
INPUT
13
CLOCK_IN_A
Clock Input, High Impedance
14
ANLG_GND
POWER
15
CLOCK_IN_B
Clock Input, High Impedance
16
C8_B
INPUT
17
C4_B
INPUT
http://onsemi.com
5
NCN6004A
PIN DESCRIPTION (continued)
Pin 18 Symbol RESET_B Type INPUT Description The signal present on this pin is translated to the RST pin of the external smart card #B. The CS signal must be Low to valid the RESET function, regardless of the selected card. Assuming the mP provides two independent lines to control the RESET pins, and MUX_MODE = Low, the NCN6004A can control two cards simultaneously. When MUX_MODE = High, this pin is internally disable, a pull up resistor is connected to VCC, (regardless of the logic state of EN_RPU), and the access to card B takes place by RESET_A associated with CARD_SEL selection bit. The associated pull up resistor is either connected to VCC (EN_RPU = H) or disconnected when EN_RPU = Low. This pin carries the data transmission between an external microcontroller and the external smart card #B. A built-in bi-directional level translator adapts the signal flowing between the card and the MCU. The level translator is enabled when CS = Low. The signal present on this pin is latched when CS = High. Since a dedicated line is used to communicate the data between the mP and the smart card, (assuming MUX_MODE = Low) the user can activate the two channels simultaneously, assuming the mP provides a pair of I/O lines. When MUX_MODE = High, this pin is internally disable, the pull up resistor is connected to VCC, (regardless of the logic state of EN_RPU), and the access to card B takes place by I/O_A associated with CARD_SEL selection bit. This pin senses the signal coming from the external smart card connector to detect the presence of card #A. The polarity of the signal is programmable as Normally Open or Normally Close switch. The logic signal will be activated when the level is either Low or High, with respect to the polarity defined previously. By default, the input is Normally Open. A built-in circuit prevents uncontrolled short pulses to generate an INT signal. The digital filter eliminates pulse width below 50ms (see spec). This pin controls the card #A C8 contact, according to the ISO7816 specifications. A built-in level shifter is used to adapt the card and the mC, regardless of the power supply voltage of each signals. The signal present at this pin is latched upon either CARD_SEL =L, or CS = H or PGM = L, and resume to a transparent mode when card #A is selected and operates in the transfer mode.The pin is hardwired to zero, the bias being provided by the VCC supply, when either the VCC voltage drops below 2.7 V, or during the CRD_VCC_A startup time. This pin controls the card #A C4 contact, according to the ISO7816 specifications. A built-in level shifter is used to adapt the card and the MCU, regardless of the power supply voltage of each signals. The signal present at this pin is latched upon either CARD_SEL = L, or CS = H, or PGM = L, and resume to a transparent mode when card #A is selected and operates in the transfer mode. The pin is hardwired to zero, the bias being provided by the VCC supply, when either the VCC voltage drops below 2.7 V, or during the CRD_VCC_A startup time. This pin is connected to the external smart card #A to support the RESET signal. A built-in level shifter is used to adapt the card and the MCU, regardless of the power supply voltage of each signals. The signal present at this pin is latched upon either CARD_SEL = Low, or when CS or PGM returns to a High, and resume to a transparent mode when card #A is selected. The pin is hardwired to zero, the bias being provided by the VCC supply, when either the VCC voltage drops below 2.7 V, or during the CRD_VCC_A startup time. This pin carries the data serial connection between the external smart card #A and the microcontroller. A built-in bidirectional level shifter is used to adapt the card and the MCU, regardless of the power supply voltage of each signals. This pin is biased by a pull up resistor connected to CRD_VCC_A. When CS = High, the CRD_IO_A holds the previous I/O logic state and resume to a normal operation when this pin is reactivated. The pin is hardwired to zero, the bias being provided by the VCC supply, when either the VCC voltage drops below 2.7 V, or during the CRD_VCC_A start-up time. This pin carries the power current flow coming from the built in DC/DC converters. It is associated with the external card # A. It must be connected to the system Ground and care must be observed at PCB layout level to avoid the risk of spike voltages on the logic lines. Connects one side of the external DC/DC converter inductor #A (Note 1). Connects one side of the external DC/DC converter inductor #A (Note 1).
19
I/O_B
INPUT/OUTPUT
20
CRD_DET_A
INPUT
21
CRD_C8_A
OUTPUT
22
CRD_C4_A
OUTPUT
23
CRD_RST_A
OUTPUT
24
CRD_IO_A
INPUT/OUTPUT
25
PWR_GND
POWER
26 27
L2_A L1_A
POWER POWER
1. The external inductors shall preferably have the same values. Depending upon the power absorbed by the load, the inductor can range from 10 mH to 47 mH. To achieve the highest yield, the inductor shall have an ESR < 1.0 W.
http://onsemi.com
6
NCN6004A
PIN DESCRIPTION (continued)
Pin 28 Symbol PWR_VCC_A Type POWER Description This pin is connected to the positive external power supply. The device sustains any voltage from +2.7 V to +5.5 V. This voltage supplies the NCN6004A internal circuits and is regulated by the internal DC/DC converter to provide the DC voltage to the external card. A high quality capacitor must be connected across pin 28 and PWR_GND, 10 mF/6.0 V ceramic X7R or X5R type is recommended. Note: The voltage present at pin 28 and 33 must be equal to the voltage present at pin 42. This pin provides the power supply to the external smart card #A. The VCC voltage is defined by programming the NCN6004A accordingly. Since the cards have independent DC/DC converter, the output voltage can have any value independently from CARD_B. A high quality, low ESR capacitor is mandatory to achieve the VCC specifications. Using two 4.7 mF/6.0 V ceramic X7R or X5R capacitors in parallel is recommended. This pin is connected to the CLK external smart card #A pin. The signal comes from the built-in frequency divider dedicated to the #A card. The clock is selected and controlled by setting the logic inputs according to Table 1. The slope of the output clock can be selected between one of the two programmable mode: SLOW or FAST (Table 8). The pin is hardwired to zero, the bias being provided by the VCC supply, when either the VCC voltage drops below 2.7 V, or during the CRD_VCC_A startup time. This pin is connected to the CLK external smart card #B pin. The signal comes from the built-in frequency divider dedicated to the #B card. The clock is selected and controlled by setting the logic inputs according to Table 1. The slope of the output clock can be selected between one of the two programmable mode: SLOW or FAST (Table 8). The pin is hardwired to zero, the bias being provided by the VCC supply, when either the VCC voltage drops below 2.7 V, or during the CRD_VCC_B startup time. This pin provides the power supply to the external smart card #B. The VCC voltage is defined by programming the NCN6004A accordingly. Since the cards have independent DC/DC converter, the output voltage can have any value independently from CARD_A. A high quality, low ESR capacitor is mandatory to achieve the VCC specifications. Using two 4.7 mF/6.0 V ceramic X7R or X5R capacitors in parallel is recommended. This pin is connected to the positive external power supply. The device sustains any voltage from +2.7 V to +6.0 V. This voltage supplies the NCN6004A internal circuits and is regulated by the internal DC/DC converter to provide the DC voltage to the external card. A high quality capacitor must be connected across pin 33 and PWR_GND, 10 mF/6.0 V ceramic X7R type is recommended. Note: The voltage present on pin 28 and 33 must be equal to the voltage present on pin 42 Connects one side of the external DC/DC converter inductor #B (Note 1). Connects one side of the external DC/DC converter inductor #B (Note 1). This pin carries the power current flow coming from the built in DC/DC converters. It is associated with the external card # B. It must be connected to the system Ground and care must be observed at PCB layout level to avoid the risk of spike voltages on the logic lines. This pin carries the data serial connection between the external smart card #B and the microcontroller. A built-in bi-directional level shifter is used to adapt the card and the MCU, regardless of the power supply voltage of each signals. This pin is biased by a pull up resistor connected to CRD_VCC_A. When CS = High, the CRD_IO_A holds the previous I/O logic state and resume to a normal operation when this pin is reactivated. The pin is hardwired to zero, the bias being provided by the VCC supply, when either the VCC voltage drops below 2.7 V, or during the CRD_VCC_B startup time. This pin is connected to the external smart card #B to support the RESET signal. A built-in level shifter is used to adapt the card and the MCU, regardless of the power supply voltage of each signals. The signal present at this pin is latched upon either CARD_SEL or CS or PGM positive going transient and resume to a transparent mode when card #B is selected. The pin is hardwired to zero, the bias being provided by the VCC supply, when either the VCC voltage drops below 2.7 V, or during the CRD_VCC_B startup time.
29
CRD_VCC_A
POWER
30
CRD_CLK_A
OUTPUT
31
CRD_CLK_B
OUTPUT
32
CRD_VCC_B
POWER
33
PWR_VCC_B
POWER
34 35 36
L2b L1b PWR_GND
POWER POWER POWER
37
CRD_IO_B
INPUT/OUTPUT
38
CRD_RST_B
OUTPUT
1. The external inductors shall preferably have the same values. Depending upon the power absorbed by the load, the inductor can range from 10 mH to 47 mH. To achieve the highest yield, the inductor shall have an ESR < 1.0 W.
http://onsemi.com
7
NCN6004A
PIN DESCRIPTION (continued)
Pin 39 Symbol CRD_C4_B Type OUTPUT Description This pin controls the card #B C4 contact, according to the ISO specification. A built-in level shifter is used to adapt the card and the MCU, regardless of the power supply voltage of each signals. The signal present at this pin is latched upon either CARD_SEL or CS or PGM positive going transient and resume to a transparent mode when card #B is selected. The pin is hardwired to zero, the bias being provided by the VCC supply, when either the VCC voltage drops below 2.7 V, or during the CRD_VCC_B startup time. This pin controls the card #B C8 contact, according to the ISO specification. A built-in level shifter is used to adapt the card and the MCU, regardless of the power supply voltage of each signals. The signal present at this pin is latched upon either CARD_SEL or CS or PGM positive going transient and resume to a transparent mode when card #B is selected. The pin is hardwired to zero, the bias being provided by the VCC supply, when either the VCC voltage drops below 2.7 V, or during the CRD_VCC_B startup time. This pin senses the signal coming from the external smart card connector to detect the presence of card #B. The polarity of the signal is programmable as Normally Open or Normally Close switch. The logic signal will be activated when the level is either Low or High, with respect to the polarity defined previously. By default, the input is Normally Open. A built-in circuit prevents uncontrolled short pulses to generate an INT signal. The digital filter eliminates pulse width below 50 ms. This pin is connected to the positive external power supply. The device sustains any voltage from +2.7 V to +5.5 V. This voltage supplies the NCN6004A internal Analog and Logic circuits. A high quality capacitor must be connected across this pin and ANLG_GND, 10 mF/6 V is recommended. A set of extra pins (28 and 33) are provided to connect the power supply to the internal DC/DC converter. Note: The voltage present at pin 28 and 33 must be equal to the voltage present at pin 42 This pin is the ground reference for both analog and digital signals and must be connected to the system Ground. Care must be observed to provide a copper PCB layout designed to avoid small signals and power transients sharing the same track. Good high frequency techniques are strongly recommended. This pin selects the mode of operation of the card signals from the MPU side. When MUX_MODE = Low, all the card signals are fully de-multiplexed and data transfers can take place with both cards simultaneously. On top of that, both cards can be accessed during the programming sequence, assuming the external microcontroller is capable to run multi tasks software. When MUX_MODE = High, all the card signals are multiplexed and the communications with the cards shall take place in a sequential mode. The card is selected by setting CARD_SEL high or Low. The internal logic will disable the CARD_B inputs and use CARD_SEL inputs as a single channel to controls both output smart cards sequentially when MUX_MODE = H. Moreover, when MUX_MODE = High, all the B channel mP dedicated pins, except CLOCK_IN_B, pin 15, are forced to a high level by means of internal pull up resistors. It is not necessary to connect these pins (16, 17, 18 and 19) to an external bias voltage, but it is mandatory to avoid any connections to ground. On the other hand, in this case the internal pull up resistor connected across I/O_A, pin 9 and VCC is automatically disconnected to avoid a current overload on the I/O line. This pin provides a logic input to valid or not the internal pullup resistors connected across each I/O, RESET, C4 and C8 lines and ANLG_VCC. When EN_RPU = High, the pull up resistors are connected When EN_RPU = Low, the pull up resistors are disconnected and it is up to the designer to set up the external resistor to cope with the ISO/EMV specifications. The logic signal must be set up prior to apply the ANLG_VCC supply. Once the logic mode has been acknowledged by the internal Power On reset, it cannot be changed until a new startup sequence is launched. This pin provides a logic state related to the card [A or B] insertion, the VCC_OK, the CRD_VCC value and the current overflow powered to either card [A or B]. The internal register can be read when PGM = High. The logic level is forced to High when the input voltage drops below the Vbat min (2.0 V), thus reducing the stand by current, assuming the STATUS pin is not pulled down externally. The associated pullup resistor is either connected to VCC (EN_RPU = H) or disconnected when EN_RPU = Low.
40
CRD_C8_B
OUTPUT
41
CRD_DET_B
INPUT
42
ANLG_VCC
POWER
43
ANLG_GND
GROUND
44
MUX_MODE
INPUT
45
EN_RPU
INPUT
46
STATUS
OUTPUT
http://onsemi.com
8
NCN6004A
PIN DESCRIPTION (continued)
Pin 47 Symbol INT Type OUTPUT Description This pin is activated LOW when a card has been inserted and detected in either of the external ports. The signal is reset by either a positive going transition on pin CS, or by a High level on pin PWR_ON combined with CS = Low. Similarly, an interrupt is generated when either one of the CRD_VCC output is overloaded. On the other hand, the pin is forced to a logic High when the input voltage VCC drops below 2.0 V min. The associated pull up resistor is either connected to VCC (EN_RPU = H) or disconnected when EN_RPU = Low. This pin is the ground reference for both analog and digital signals and must be connected to the system Ground. Care must be observed to provide a copper PCB layout designed to avoid small signals and power transients sharing the same track. Good high frequency techniques are strongly recommended.
48
ANLG_GND
GROUND
MAXIMUM RATINGS (Note 2)
Rating Power Supply Input Supply Voltage Vin Power Supply Input Current Digital Input Pins Digital Output Pins Card Interface Pins ESD Capability, Human Body Model (Note 3) Standard Pins Card Interface Pins (Card A or B) TQFP48 Power Dissipation @ Tab = +85C Thermal Resistance Junction-to-Air Operating Ambient Temperature Range Operating Junction Temperature Range Maximum Junction Temperature (Note 4) Storage Temperature Range PD RJqA TA TJ TJmax Tag 800 50 -40 to +85 -40 to +125 +150 -65 to +150 mW C/W C C C C Symbol VCC Digital Input Pins IVCC Vin In Vout Iout Vcard Icard VESD 2 8 kV kV Value 6 -0.5 V < Vin< VCC +0.5 V, but < 6.0 V 500 -0.5 < VCC or VCC < 5.5 "5 -0.5 < VCC or VCC < 5.5 "10 -0.5V < Vcard < CRD_VCC +0.5V 15 mA (internally limited) Unit V V mA V mA V mA V mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 2. Maximum Electrical Ratings are defined as those values beyond which damage(s) to the device may occur at TA = +25C. 3. Human Body Model, R = 1500 W, C = 100 pF. 4. Absolute Maximum Rating beyond which damage(s) to the device may occur.
http://onsemi.com
9
NCN6004A
POWER SUPPLY SECTION General test conditions, unless otherwise specified: Operating temperature: -25C < TA < +85C,
VCC = +3.0 V, CRD_VCC_A = CRD_VCC_B = +5.0 V. Rating Iout = 2 x 65 mA (both external cards running simultaneously) @ 3.0 V < VCC < 5.5 V Iout = 2 x 55 mA per pin (both external cards running) Vout defined @ CRD_VCC = 3.0 V @ 3.0 V < VCC < 5.5 V Iout = 2 x 35 mA per pin (both external cards running) Vout defined @ CRD_VCC = 1.80 V @ 3.0 V < VCC < 5.5 V Output Card Supply Voltage Ripple (per CRD_VCC outputs) @ : Lout = 22 mH, LESR < 2.0 W, Cout = 10 mF per CRD_VCC (Note 5) Iout = 35 mA, Vout = 1.80 V Iout = 55 mA, Vout = 3.0 V Iout = 65 mA, Vout = 5.0 V DC/DC Dynamic Inductor Peak Current @ Vbat = 5.0 V, Lout = 22 mH, Cout = 10 mF CRD_VCC = 1.8 V CRD_VCC = 3.0 V CRD_VCC = 5.0 V Standby Supply Current Conditions (Note 5): ANLG_VCC = PWR_VCC = 3.0 V PWR_ON = H, STATUS = H, CS = H Card A and Card B CLOCK_IN = H, I/O = H, RESET = H All Logic Inputs = H, Temperature range = 0C to +50C ANLG_VCC = PWR_VCC = 5.0 V Temperature range -25C to +85C All other test conditions identical ANLG_VCC = PWR_VCC = 1.8 V Temperature range -25C to +50C All other test conditions identical Note: This parameter is guaranteed by design, not production tested. Operating Supply Current ANLG_VCC = PWR_VCC = 5.5 V @ CRD_VCC_A/B = 5.0 V @ CRD_VCC_ A/B = 3.0 V @ CRD_VCC_ A/B = 1.85 V ANLG_VCC = PWR_VCC = 3.3 V @ CRD_VCC_A/B = 5.0 V @ CRD_VCC_ A/B = 3.0 V @ CRD_VCC_ A/B = 1.85 V PWR_ON = H, CS = H, CLK_A = CLK_B = Low, all card pins unloaded Vbat Under Voltage Detection Positive Going Slope Vbat Under Voltage Detection Negative Going Slope Vbat Under Voltage Detection Hysteresis Note: The voltage present in pins 28 and 33 must be equal to or Note: lower than the voltage present in pin 42. Output Continuous Current Card A or Card B (both cards can be operating simultaneously) @ 3.0 < VCC < 5.5 V Output Voltage = 1.85 V Output Voltage = 3.0 V Output Voltage = 5.0 V Output Over Current Limit (A or B) Vbat = 3.3 V, CRD_VCC = 1.8 V, 3.0 V or 5.0 V Vbat = 5.0 V, CRD_VCC = 1.8 V, 3.0 V or 5.0 V Output Over Current Time Out Per Card Output Card Supply Turn On Time @ Lout = 22 mF, Cout = 10 mF Ceramic. VCC = 2.7 V, CRD_VCC = 5.0 V (A or B) VbatLH VbatLL VbatHY 42 2.1 2.0 - IDDop 42, 28, 33 0.7 0.7 0.7 Symbol CRD_VCC CRD_VCC CRD_VCC Pin 29, 32 4.6 29, 32 2.7 29, 32 1.65 - 1.95 mV VORA VORB Iccov 29 32 29, 32 - - - IDD 42, 28, 33 - - - 20 - - 200 280 430 - - - mA - - - - - - 50 50 50 mA - 3.3 V - 5.4 V Min Typ Max Unit V
- -
50 - - 5.0 - mA
- -
0.2 0.2 0.2 - - 100 2.7 2.6 - V V mV
Iccp
31, 42 35 55 65
mA
Iccov
31, 42 100 150 mA ms ms 500
Itdoff VCCTON
31, 42 31, 42
4.0
5. Assuming ANLG_VCC and PWR_VCC pins are connected to the same power supply.
http://onsemi.com
10
NCN6004A
POWER SUPPLY SECTION General test conditions, unless otherwise specified: Operating temperature: -25C < TA < +85C,
VCC = +3.0 V, CRD_VCC_A = CRD_VCC_B = +5.0 V. (continued) Rating Output Card Supply Shut Off Time @ Cout = 10 mF, ceramic. VCC = 2.7 V, CRD_VCC = 5.0 V, VCCOFF < 0.4 V (A or B) DC/DC Converter Operating Frequency (A or B) Symbol VCCTOFF Pin 31, 42 100 FSW 31, 42 600 250 kHz Min Typ Max Unit ms
5. Assuming ANLG_VCC and PWR_VCC pins are connected to the same power supply.
DIGITAL INPUT/OUTPUT SECTION
2.70 < VCC < 5.50 V, Normal Operating Mode (-25C to +85C ambient temperature, unless otherwise noted) Rating A0, A1, A2, A3, CARD_SEL, PWR_ON, PGM, CS, MUX_MODE, EN_RPU, RESET_A, RESET_B, C4_A, C8_A, C4_B, C8_B High Level Input Voltage Low Level Input Voltage Input Capacitance Symbol Pin 1, 2, 3, 4, 5, 6, 7, 8, 44, 45, 10, 18, 11, 12, 16, 17 46, 47 VOH VOL trsta, trint tfsta, tfint FCLKINA FCLKINB trioA, trioB tfioA, tfioB RSTA RINT RIOA RIOB RRSTA RRSTB RC4A RC8A RC4B RC8B RCS RDETA RDETB 13 15 9, 19 46 47 9 19 10 18 11 12 17 16 7 20 41 35 35 14 14 60 60 60 60 60 60 60 50 50 20 20 100 100 100 100 100 100 100 500 500 35 35 Vbat -1.0 V 0.40 5 100 40 40 0.8 0.8 kW kW kW kW kW kW kW kW kW kW kW kW kW ms ns MHz MHz ms Min Typ Max Unit
VIH VIL Cin
0.7 * Vbat
Vbat 0.3 * Vbat 10
V V pF
STATUS, INT Output High Voltage @ IOH = -10 mA Output Low Voltage @ IOH = 200 mA STATUS, INT Output Rise Time @ Cout = 30 pF Output Fall Time @ Cout = 30 pF CLOCK_A Asynchronous Input Clock @ DC = 50% "1% CLOCK_B Asynchronous Input Clock @ DC = 50% "1% I/O_A, I/O_B, both directions @ Cout = 30 pF I/O Rise Time I/O Fall Time STATUS Pull Up Resistance INT Pull Up Resistance I/O_A Pull Up Resistance I/O_B Pull Up Resistance RESET_A Pull Up Resistance RESET_B Pull Up Resistance C4_A Pull Up Resistance C8_A Pull Up Resistance C4_B Pull Up Resistance C8_B Pull Up Resistance CS Pull Up Resistance CRD_DET_A and CRD_DET_B Pull Up Resistance
V
http://onsemi.com
11
NCN6004A
CARD INTERFACE SECTION @ 2.70 < VCC < 5.50 V, Normal Operating Mode (-25C to +85C ambient temperature, unless otherwise noted) CRD_VCC_A = CRD_VCC_B = 1.8 V or 3.0 V or 5.0 V
Rating CRD_RST_A, CRD_RST_B Output Voltage Output RST High Level @ Irst = -200 mA Output RST Low Level @ Irst = 200 mA CRD_RST_A, CRD_RST_B Rise and Fall time RST Rise Time @ Cout = 30 pF RST Fall Time @ Cout = 30 pF CRD_CLK_A, CRD_CLK_B Output Clock Output Operating Clock Card A and Card B Output Operating Clock DC, Card A and Card B (Input DC = 50%, "1%) Note: This parameter is guaranteed by design, functionality 100% tested at production. Output Operating Clock Rise Time SLOW Mode Card A and Card B Output Operating Clock Fall Time SLOW Mode Card A and Card B Output Operating Clock Rise Time FAST Mode Card A and Card B Output Operating Clock Fall Time FAST Mode Card A and Card B Output Clock High Level, Card A and Card B, @ Iclk = -200 mA Output Clock Low Level, Card A and Card B, @ Iclkc = 200 mA CRD_IO_A, CRD_IO_B Data Transfer Data Transfer Frequency, Card A and Card B Data Rise Time, Card A and Card B, @ Cout = 30 pF Data Fall Time, Card A and Card B, @ Cout = 30 pF Data Output High Level, Card A and Card B @ Icrd_io = -20 mA Data Output Low Level, Card A and Card B @ Icrd_io = 20 mA CRD_IO_A and CRD_IO_B Output Voltages I/O_A = I/O_B = 0, IOL = 500 mA CRD_C4_A, CRD_C4_B Output Voltages Output C4 High Level @ Irst = -200 mA Output C4 Low Level @ Irst = 200 mA CRD_C4_A, CRD_C4_B Rise and Fall time C4 Rise Time @ Cout = 30 pF C4 Fall Time @ Cout = 30 pF CRD_C8_A, CRD_C8_B Output Voltages Output C4 High Level @ Irst = -200 mA Output C4 Low Level @ Irst = 200 mA CRD_C8_A, CRD_C8_B Rise and Fall Time C8 Rise Time @ Cout = 30 pF C8 RST Fall Time @ Cout = 30 pF Pull Up resistance, CS = Low, PWR_ON = High CRD_IO_A CRD_IO_B Card Detection Bias Pull Up Current, Card A or Card B CRD_DET_A, CRD_DET_B Card Insertion/Extraction Negative Going Input Low Voltage Card Detection Insertion/Extraction Digital Filtering Delay CRD_DET_A CRD_DET_B CARD_A or CARD_B short circuit current: CRD_IO, CRD_RST, CRD_C4, CRD_C8 CRD_CLK (According to ISO and EMV specifications) Symbol VOH VOL Pin 23, 38 23, 38 Min CRD_VCC-0.5 0 Typ Max CRD_VCC 0.4 Unit V V
trrst tfrst FclkA, FclkB
23, 38 23, 38 30, 31 45
100 100 20 55
ns ns MHz %
trclka, trclkb tfclka, tfclkb trclka, trclkb tfclka, tfclkb VOH VOL 24, 37 FIOA, FIOB trioa, triob tfioa, tfiob VOH VOL 24, 37 VOL 22, 39 VOH VOL trc4 tfc4 21, 40 VOH VOL trc8 tfc8 ROLA ROLB IDETA IDETB VILDETA VILDETB tdcina tdcinb Ishort Ishortclk 24 37 20 41 20 41 20 41 0 0 50 50 14 14 20 20 15 15 CRD_VCC-0.5 0 CRD_VCC-0.5 0 400 CRD_VCC-0.5 0 CRD_VCC-0.5 0
16 16 4 4 CRD_VCC 0.4
ns ns ns ns V V kHz ms ms V V V
0.8 0.8 CRD_VCC 0.4 0.40 CRD_VCC 0.4 100 100 CRD_VCC 0.4 100 100 35 35
V V ns ns V V ns kW
mA 0.30 * Vbat 0.30 * Vbat V ms
mA 15 70
http://onsemi.com
12
NCN6004A
DIGITAL DYNAMIC SECTION NORMAL OPERATING MODE
Rating Card Signal Sequence Interval, CRD_VCC_A and CRD_VCC_B: CRD_IO_A, CRD_RST_A, CRD_CLK_A, CRD_C4_A, CRD_C8_A CRD_IO_B, CRD_RST_B, CRD_CLK_B, CRD_C4_B, CRD_C8_B Internal RESET Delay Internal STATUS Delay Time PWR_ON Low State Pulse Width (Figure 11), Assuming CRD_VCC reservoir capacitor = 10 mF. PWR_ON High State Pulse Width (Figure 11) PWR_ON Preset Delay (Figure 11) PWR_ON Programming Hold Time (Figure 11) PWR_ON to CARD_SEL Change Delay Time (Figure 12) PGM to PWR_ON Delay Time (Figure 12) PWR_ON internal Set/Reset Pulses Width (Figure 12) Symbol tdseq Pin 24, 23, 30, 37, 38, 31 Min Typ 0.5 0.5 1.0 46 8 5 tpwrset tpwrpre tpwrhold tcseldly tpgmdly tpwrp 8 5, 7, 8 5, 7, 8 5, 6, 8 5, 6, 8 8 200 300 100 100 300 20 ns ns ns ns ns ns 1.0 Max 2 2 ms ms ms Unit ms
tdreset tdready tpwrlow
DIGITAL DYNAMIC SECTION PROGRAMMING MODE
Rating Data Set-up Time, Time Reference = PGM, A0, A1, A2, A3, CARD_SEL, and CS. Data Signal Rise and Fall Time Data Hold Time, Time Reference = PGM, A0, A1, A2, A3, CARD_SEL, and CS. Chip Select CS Low State Pulse Width CS Signal Rise and Fall Time Symbol tsmod tsmodtr tsmod tsmodtr twcs trfcs 8, 46, 1, 2, 3, 4, 5, 6 7 100 50 300 50 Pin 8, 46, 1, 2, 3, 4, 5, 6 Min 100 50 Typ Max Unit ns ns ns ns ns ns
http://onsemi.com
13
NCN6004A
PROGRAMMING AND STATUS FUNCTIONS The NCN6004A includes a programming interface and a status interface. Figure 4 illustrates the sequence one must follow to enter and exit the programming mode. Table 1 and Table 2 provide the logical functions associated with the
Example: Set CRD_VCC_A = 3.0 V A0 A1 A2 A3 CARD_SEL
input and output signals. The parameters are latched upon the rising edge of the PGM signal, the CS pin being held low. Any number of programming sequences can be performed while the CS pin is Low, but the minimum timings must be observed.
Example: Set CRD_CLK_B = 1/8
Parameters are latched upon PGM rise slope
PGM CS
tsprg
twcs
thprg
Figure 4. Programming Sequence
On the other hand, since the programming data are latched upon the rising edge of the PGM signal, the most up to date selected card (using CARD_SEL = H or L) is used to activate the associated card. Consequently, when both cards must be updated with the same programmed content, a dual PGM sequence must be carried out, changing the CARD_SEL signal during the High level state of the PGM pin. Although selecting a card in possible during the same Chip Select sequence (as depicted here above), the user must
Table 1. Programming and Reading Basic Functions
Pin 7 46 1 2 3 4 5 6 Name CS STATUS A0 A1 A2 A3 CARD_SEL PGM Select #A #B 0 - 0/1 0/1 0/1 0/1 0/1 0/1 Select VCC ON/OFF 0 - 0/1 0/1 0/1 0/1 0/1 0/1 Program CLOCK_IN 0 - 0/1 0/1 0/1 0/1 0/1 0/1
make sure that no data will be present to a card not ready for such a function. As a matter of fact, all the card signals are routed to the selected card immediately after a CARD_SEL change, the NCN6004A taking no further logic control prior to activate the swap. To avoid any risk, one can run a sequence with the selected card, return CS to High, change the CARD_SEL according to the expected card selection, and pull CS to Low to activate the selected card.
Poll Card Status #A or #B 0 READ 1 1 X X 0/1 1
Poll ICC Overload #A or #B 0 READ 0 1 X X 0/1 1
http://onsemi.com
14
EEEEE EEEEE EEEEE EEEEE EEEEE EEEEE EEEEE EEEEE EEEEE EEEEE
ANLG_VCC Input Voltage OK 0 READ 0 0 X X 0/1 1
EEEE EEEE EEEE EEEE EEEE EEEE EEEE EEEE EEEE EEEE
EEEEE EEEEE EEEEE EEEEE EEEEE EEEEE EEEEE EEEEE EEEEE EEEEE
NCN6004A
Table 2. Programming Functions (Conditions at start-up are in Bold)
(HEX) PGM A3 00 01 02 03 00 01 02 03 04 05 06 07 04 05 06 07 08 09 0A 0B 08 09 0A 0B 0C OD 0C 0D 0E 0F 0E 0F 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 1 A0 CARD_SEL 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 - - - - - - - - CLK_D_A CLK_D_B - - - - CLK_D_B CLK_D_A - - - - CRD_VCC #A 1.80 V 3.0 V 5.0 V - - - - - - - - - - - - - - - - - - - - - - - - CRD_VCC #B - - - - 1.80 V 3.0 V 5.0 V - - - - - - - - - - - - - - - - - - - - CRD_CLK CRD_CLK #A #B - - - - - - - - 1/1 1/2 1/4 1/8 - - - - START STOPL STOPH - - - - - - - - - - - 1/1 1/2 1/4 1/8 - - - - START STOPL STOPH - - - - - - - - - - - CRD_DET #A - - - - - - - - - - - - - - - - - - - - - - - - NO NC - NO NC - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - FAST - - - FAST - - - - - - - - CRD_DET #B - - - CLOCK SLOPE - - - SLOW - - - SLOW - - -
http://onsemi.com
15
NCN6004A
Table 3. Status Pins Data
STATE (HEX) 00 01 02 03 PGM 1 1 1 1 A3 X X X X A2 X X X X A1 0 0 1 1 A0 0 1 0 1 CARD_SEL X 1 1 1 STATUS #A Vcc_V bat_OK Pass = Low VCC_OK Fail = High CRD_VCC_A In Range Pass = High Fail =Low CRD_VCCA Overloaded Pass = High Fail = Low CRD_DET_A Card Present = High VCC_OK Pass = Low VCC_OK Fail = High CRD_VCC_B In Range Pass = High Fail =Low CRD_VCC_B Overloaded Pass = High Fail = Low CRD_DET_A Card Present = High STATUS #B
00 01 02 03
1 1 1 1
X X X X
X X X X
0 0 1 1
0 1 0 1
X 0 0 0
*The STATUS register is not affected when the NCN6004A operates in any of the programming mode. Initialized conditions upon start-up are depicted by bold characters in Table 2 and Table 4. Typical ANLG_VCC Operating Voltage Min. ANLG_VCC Under Voltage Max. ANLG_VCC Under Voltage 3.30 V 2.70 V 2.10 V 2.00 V Vbat Vbat_OK Vbat STATUS
The input power supply voltage monitoring applies to the card selected.
Figure 5. Reading ANLG_VCC Status (monitoring ANLG_VCC input voltage)
SYSTEM STATES UPON UPON START-UP
Table 4. Operating Conditions Upon Start-up
CRD_VCC_A CRD_VCC_B CRD_CLK_A CRD_CLK_B CRD_CLK_A CRD_CLK_B CRD_CLK_A CRD_CLK_B CLOCK Route 3.0 V 3.0 V 1/1 Ratio 1/1 Ratio START (clock is valid) START (clock is valid) Low Speed Slope Low Speed Slope Direct (CLK_A A, CLK_B B)
Depending upon the logic state at turn on present on pin 44, the system will run into a parallel mode (MUX_MODE = L) or a multiplexed mode (MUX_MODE = H). It is not possible to change the logic state once the system is running. Similarly, depending upon the logic state present pin 45, the internal pull up resistors (I/O_A and I/O_B line) will be either connected to ANLG_VCC voltage (EN_RPU = H) or disconnected (EN_RPU = L). It is not possible to change this operating condition once the system is running.
http://onsemi.com
16
NCN6004A
PARALLEL/MULITPLEXED OPERATION MODES The logic input MUX_MODE, pin 44, provides a way to select the operation mode of the NCN6004A. Depending upon the logic level, the device operates either in a parallel mode (all the card pins, on the mP side, are fully independent)
RESET_A C4_A C8_A I/O_A 10 11 12 9 Q4
or in multiplexed mode (all the logic card pins, on the mP side, share a common bus). Figure 6 shows a simplified schematic of the multiplex circuit built in the NCN6004A chip.
GATING CARD_A BUFFERS CARD_A
23 22 21 24
I/O_A BUFFER
I/O_B
19 A 18 17 16 15 A Q2 A Q3 B GATING CARD_B
I/O_B BUFFER
37
REST_B C4_B C8_B MUX_MODE
Q1 B
BUFFERS CARD_B
38 39 40
B MULTIPLEXER
CARD_SEL CLK_IN_A
15 13 CLOCK DIVIDERS & MULTIPLEXER CLK_A BUFFER 30
CLK_IN_B
15
CLK_B BUFFER
31
Figure 6. Simplified MUX_MODE Logic and Multiplex Circuit
In both case, the device is programmed by means of the common logic controls pins (A0, A1, A2, A3, PGM, PWR_ON, CARD_SEL and CS). On the other hand, the logic status returned by the interface (STATUS pin 46) is shared by the two channels and can be read independently by setting CARD_SEL accordingly. The card related signals connected on the mC side are multiplexed or independent, depending upon the MUX_MODE state as described here below.
MUX_MODE = Low " PARALLEL MODE
transaction can take place at the same time and processed independently. Of course, the microcontroller must have the right data bus available to handle this process. However, it is not possible to change the operating mode once the system has been started. If such a function is needed, one must pull down the related NCN6004A power supply, change the MUX_MODE logic level, and re-start the interface.
MUX_MODE = High " MULTIPLEXED MODE
When pin 44 is low, the device operates in the parallel mode. The transfer gate Q4 and the multiplexer circuit are disconnected and all the data will be carried out through their respective paths. The switches Q1, Q2 and Q3 are flipped to the B position, thus providing a direct connection from port B control signals to CARD_B All the CARD_A and CARD_B signals are independent and both cards can operate simultaneously, the data
When pin 44 is High, the device operates in a multiplexed mode and all the card signals are shared between CARD_A and CARD_B, except the input clocks which are independent at any time. The RST_B, C4_B and C8_B pins are preferably left open at PCB level. The I/O_B pin must be left open and cannot be connected to any external signal or bias voltages. The transfer gate Q4 is switched ON and, depending upon the CARD_SEL logic level, the I/O data will be transferred
http://onsemi.com
17
NCN6004A
to either CARD_A or CARD_B. It is neither possible to connect directly I/O_A to I/O_B nor to connect the I/O_B pin to ground or voltage supply. The multiplexer is activated and the CARD_SEL signal is used to select the card in use for a given transaction. The switches Q1, Q2 and Q3 and swapped to the A position, thus providing a path for the control signals applied to the CARD_A side. When the CARD_SEL signal flips from one card to the other, the previous logic states of the on going card are latched in the chip and the related output card pin are maintained at the appropriate levels. When the system resumes to the previous card, the latches return to the transparent operation and the signals presented by the mP take priority over the previously latched states. On the other hand, the input clocks (CLK_IN_A and CLK_IN_B) are maintained independent and can be routed to either CARD_A or CARD_B according to the programming functions given in Table 2.
V
CARD POWER SUPPLY TIMING When the PWR_ON signal is high, the associated CRD_VCC_A or CRD_VCC_B power supply rise time depends upon the current capability of the DC/DC converter together with the external inductors L1/L2 and the reservoir capacitor connected across each card power supply pin and GROUND. On the other hand, at turn off, the CRD_VCC_A and CRD_VCC_B fall times depend upon the external reservoir capacitor and the peak current absorbed by the internal NMOS device built across each CRD_VCC_A/ CRD_VCC_B and GROUND. These behaviors are depicted by Figure 7, assuming a 10 mF output capacitor. Since none of these parameters can have infinite values, the designer must take care of these limits if the tON or the tOFF provided by the data sheets does not meet his requirement.
CRD_VCC = 5 V CRD_VCC = 4.75 V
CRD_VCC = 0.40 V 500 ms Max Turn ON 250 ms Max Shut OFF t
Figure 7. Card Power Supply Turn ON and Shut OFF Typical Timings
POWER DOWN OPERATION The power down mode can be initiated by either the external MPU or by the internal error condition. The communication session is terminated immediately, according to the ISO7816-3 sequence. On the other hand, the MPU can run the Stand By mode by forcing CS = H, leaving the chip in the previous operating mode.
When the card is extracted, the interface will detect the operation and will automatically run the Power Down Sequence of the related card as described by the ISO/CEI 7816-3 sequence depicted in Figure 8 and illustrated by the oscillogram in Figure 9.
CARD EXTRACTION DETECTED CRD_DET CRD_RST Force RST to Low Force CLK to Low, unless it is already in this state Force C4 and C8 to Low Force CRD_IO to Low Shut Off the CRD_VCC Supply CRD_CLK CRD_C4 CRD_C8 CRD_IO CRD_VCC Internal Delay 400 ns typ. T
Figure 8. Card Power Down Sequence
http://onsemi.com
18
NCN6004A
On the other hand, the Power Down sequence is automatically activated when the Vbat voltage drops below the VCC_OK level, regardless of the logic conditions present on the control pins, or when the related CRD_VCC_x output voltage reaches the overload condition.
Figure 9. Power Down Sequence
Figure 10. Power Down Sequence: Timing Details
http://onsemi.com
19
NCN6004A
CARD DETECTION The card detector circuit provides a constant low current to bias the CRD_DET_A and CRD_DET_B pins, yielding a logic High when no card is present and the external switch is Normally Open type. The internal logic associated with pins 20 and 41 provides a programmable selection of the slope card detection. The transition is filtered out by the internal digital filter circuit, avoiding false interrupt. In addition to the typical 50 ms delay, the MPU shall provide an additional delay to cope with the mechanical stabilization of the card interface (typically 1 ms), prior to valid the CRD_VCC_A or CRD_VCC_B supply.
INTERRUPT ACKNOWLEDGE 50 ms < T < 150 ms CRD_DET_A INT CS PGM A0 A1 A2 A3 CARD_SEL STATUS CLEAR INTERRUPT CARD PRESENT: STATUS = 1 CLEAR INTERRUPT CARD NOT PRESENT: STATUS = 0 High High High IRRELEVANT IRRELEVANT High = Card A
When a card is inserted, the detector circuit asserts INT = Low as depicted before, the external mP being responsible to clear the interrupt signal, taking the necessaries actions. When the NCN6004A detects a card extraction, the power down sequence is automatically activated for the related interface section, regardless of the PWR_ON state, and the INT pin is asserted Low. It is up to the external MPU to clear this interrupt by pulsing the CS pin.
CARD IDENTIFICATION & PROCESSING
CARD EXTRACTED 50 ms < T < 150 ms
Figure 11. Typical Interrupt Sequence
The interrupt signal can be cleared either by a positive going slope on the Chip Select pin as depicted in Figure 11, or by forcing the PWR_ON signal High (keeping CS = Low) for the related card.
Table 5. Card Detection Polarity
CS 1 0 0 0 0 0 PGM X 1 0 0 0 0 A3 X X 1 1 1 1 A2 X X 1 1 1 1 A1 X X 0 0 0 0 A0 X X 0 1 0 1
The polarity of the card detection switch can be either Normally Open or Normally Close and is software controlled as defined here below and in Table 2.
CARD_SEL X X 1 1 0 0
CRD_DET_A Qn -1 Qn -1 Normally Open Normally Close Qn -1 Bn -1
CRD_DET_B Qn -1 Qn -1 Qn -1 Qn -1 Normally Open Normally Close
*The polarity change is validated upon the next positive PGM transient.
http://onsemi.com
20
NCN6004A
POWER MANAGEMENT The main purpose of the power management is to provides the necessary output voltages to drive the 1.80 V, 3.0 V or 5.0 V smart card types. On top of that, the DC/DC converter efficiency must absorb a minimum current on the Vbat supply. Beside the power conversion, in the Stand by mode (PWR_ON = L), the power management provides energy to the card detection circuit only. All the card interface pins are forced to ground potential, saving as much current as possible out of the battery supply. In the event of a power up request coming from the external MPU (CARD_SEL =H/L, PWR_ON = H, CS = L), the power manager starts the DC/DC converter related to the selected interface section. When the selected section (either CRD_VCC_A or CRD_VCC_B) voltage reaches the programmed value (1.8 V, 3.0 V or 5.0 V), the circuit activates the card signals according to the following sequence: CRD_VCC_x CRD_IO_x CRD_C4_x CRD_C8_x CRD_CLK_x CRD_RST_x The logic level of the data lines are asserted High or Low, depending upon the state forced by the external MPU, when the start-up sequence is completed. Under no situation the NCN6004A shall automatically launch a smart card ATR sequence. At the end of the transaction, asserted by the MPU (CARD_SEL = H/L, PWR_ON = L, CS = L), or under a card extraction, the ISO7816-3 power down sequence takes place: CRD_RST_x CRD_CLK_x CRD_C4_x CRD_C8_x CRD_IO_x CRD_VCC_x When CS = H, the bi-directional I/O lines (pins 9 and 19) are forced into the High impedance mode to avoid signal collision with any data coming from the external MPU. OUTPUT VOLTAGE PROGRAMMING The internal logic provides a reliable circuit to activate any of the DC/DC converters safely. In particular, the Turn On/Turn Off of these converters is edge sensitive and controlled by the rising/falling edges of the PWR_ON signal applied with Chip Select pin Low. The CARD_SEL signal is used to select either CRD_VCC_A or CRD_VCC_B as defined by the functions programming in Table 2.
CS CARD_SEL PWR_ON SET RESET see note
CRD_VCC_A
CRD_VCC_B CRD_VCC Rise Time VCCton CRD_VCC_A PWR DOWN Note : minimum 1 ms delay before to send a power Off command to the same selected output is recommended. CRD_VCC No Change VCCton VCCtoff
Figure 12. Card Power Supply Controls
Although it is possible to change the output voltage straightly from 5.0 V to 1.80 V, care must be observed as the stabilization time will be relatively long if no current is absorbed from the related output pin. According to the typical sequence depicted, it is not possible to program simultaneously the two DC/DC
converters, but two separate sequences must take place. On top of that, since the circuit is edge sensitive, the PWR_ON signal must present such a transient when a given state is expected for the converter. The PWR_ON and CS timings definitions are given in Figure 13.
http://onsemi.com
21
NCN6004A
CS
CARD_SEL tpwrpre PWR_ON SET RESET tpwrp NOTE: tpwrset: This delay is necessary to latch-up the PWR_ON condition and does not represent the CRD_VCC output voltage rise time. tpwrlow: This delay includes the internal ISO7816-3 power down sequence to make sure the DC/DC converter is fully deactivated. tpwrset tpwrlow tpwrhold
Figure 13. Power On Sequence Timings
CS
Chip Selected
CARD_SEL tcseldly tpwrhold PWR_ON tpgmdly PGM NOTE: Programming Sequence tpwrw: This delay represents the minimum pulse width needed to write the PWR_ON status into the associated DC/DC latch tpwrw
Figure 14. Power On and CARD_SEL Sequence Timings
DC/DC CONVERTER The power conversion is carried out either in step up or step down mode. The operation is fully automatic and, beside the output voltage programming, does not need any further adjustments. The simplified DC/DC converter, given in Figure 15, is based on a full bridge structure capable to handle either step up or step down power supply using an external inductor. This structure brings the capability to operate from a wide range of input voltage, while providing the accurate 1.80 V, 3.0 V or 5.0 V requested by the smart cards. Beside the accuracy, the major aim of this structure is the high efficiency necessary to save energy taken from the battery. On the other hand, using two independent converters provides a high flexibility and prevent a total system crash in the event of a failure on one of the card connected to the interface.
OPERATION
NOTE: Described operation makes reference to CARD_A and can be applied to CARD_B. The system operates with a two cycles concept:
1. Cycle 1: Q15 and Q4 are switched ON and the inductor L1 is charged by the energy supplied by the external battery. During this phase, the pairs Q1/Q16 and Q2/Q3 are switched OFF. The current flowing into the two MOSFET Q1 and Q4 is internally monitored and will be switched OFF when the Ipeak value (depending upon the programmed output voltage value) is reached. At this point, Cycle 1 is completed and Cycle 2 takes place. The ON time is a function of the battery voltage and the value of the inductor network (L and Zr) connected across pins 26/27 and 34/35. A 4 ms time out structure makes sure the system does run in a continuous Cycle 1 loop. 2. Cycle 2: Q1 and Q16 are switched ON and the energy stored into the inductor L1 is dumped into the external load through Q16. During this phase, the pair Q15/Q4 and the pair Q2/Q3 are switched OFF. The current flow period is constant (900 ns typical) and Cycle 1 repeats after this time if the CRD_VCC voltage is below the specified value.
http://onsemi.com
22
NCN6004A
When the output voltage reaches the specified value (1.80 V or 3.0 V or 5.0 V), Q1 and Q16 are switched OFF immediately to avoid over voltage on the output load. In the mean time, the two extra NMOS Q2 and Q3 are switched ON to fully discharge any current stored into the inductor, avoiding ringing and voltage spikes over the system. Figure 16 illustrates the theoretical basic waveforms present in the DC/DC converter. The control block gives the logic states according to the bits provided by the external mP. These controls bits are applied to the selected DC/DC converter to generate the programmed output voltage. The MOS drive block includes the biases necessaries to drive the NMOS and PMOS devices as depicted in the block diagram given Figure 15.
Vcc 28 10 mF C1 Vref GND MIXED LOGIC / ANALOG BLOCK G_Q1 G_Q3 L1 27 Q1 Q2 22 mH Q3 Q15
CRD_VCC_A 29 Q16 Q5 10 mF C2 26 Q4 GND R2 25 PWR_GND GND R3 GND Q7 R1 GND
PWR_ON V0 V1 CARD_SEL A0 A1 DC/DC MULTIPLEXED CONTROLS A2 A3 CS PWR_ON Overload VCC_OK LOGIC CONTROL # A
PGM
Vout
G_HIZ G_Q4 G_Q2 G_Q7 Vcc U1
Q6 Voltage Regulation Vref_1.8/3/5 V 5.0 V 5.0 V GND GND 33 Vcc 10 mF C3 Vref GND MIXED LOGIC / ANALOG BLOCK G_Q1 G_Q3 36 PWR_GND GND R7 GND Vcc U2 Q13 R8 L2 34 Q8 Q9 22 mH Q10 35 Q11 GND R6 Q14 R5 Q17 CRD_VCC 32 Q18 Q12 10 mF C4 GND R4
PWR_ON V0 V1 Overload VCC_OK LOGIC CONTROL # A
Vout
G_HIZ G_Q4 G_Q2 G_Q7
Voltage Regulation Vref_1.8/3/5 V 5.0 V 3.0 V GND
GND
Figure 15. Basic DC/DC Converter Diagram
http://onsemi.com
23
NCN6004A
Since the output inductor L1 and the reservoir capacitor C1 carry relative high peak current, low ESR devices must be used to prevent the system from poor output voltage ripple and low efficiency. Using ceramic capacitors, X5R or X7R type, are recommended, splitting the 10 mF in two separate parts when there is a relative long distance between
Charge CRD_VCC Ton Toff Q1 / Q4 Q2 / Q3 Q5/Q6 Ipeak IL CRD_VCC Voltage Regulated Vripple
the CRD_VCC_x output pin and the card VCC input. On the other hand, the inductor shall have an ESR below 1.0 W to achieve the high efficiency over the full temperature range. However, inductor with 2.0 W ESR can be used when a slight decrease of the efficiency is acceptable at system level.
CRD_VCC Charged (Time is not to scale)
Next CRD_VCC Charge
CRD_VCC
Figure 16. Theoretical DC/DC Operating
When the CRD_VCC is programmed to zero volt, or when the card is extracted from the socket, the active pull down Q5 rapidly discharges the output reservoir capacitor, making sure the output voltage is below 0.40 V when the card slides across the contacts. Based on the experiments carried out during the NCN6004A characterization, the best comprise, at time of printing this document, is to use two 4.7 mF/10 V/ceramic/X7R capacitor in parallel to achieve the CRD_VCC filtering. The ESR will not extend 50 mW
Table 6. Ceramic/Electrolytic Capacitors Comparison
Manufacturer MURATA MURATA VISHAY VISHAY Miscellaneous Type/Series CERAMIC/GRM225 CERAMIC/GRM225 Tantalum/594C/593C Electrolytic/94SV Electrolytic Low Cost Format 0805 0805 1206 1812 1812
over the temperature range and the combination of standard parts provide an acceptable -20% to +20% tolerance, together with a low cost. Table 6 shows a quick comparison between the most common type of capacitors. Obviously, the capacitor must be SMD type to achieve the extremely low ESR and ESL necessary for this application. Figure 17 illustrates the CRD_VCC ripple observed in the NCN6004A demo board running with X7R ceramic capacitors.
Max Value 10 mF/6.3 V 4.7 mF/6.3 V 10 mF/16 V 10 mF/10 V 10 mF/10 V
Tolerance -20% /+20% -20% /+20%
Typ. Z @ 500 kHz 30 mW 30 mW 450 mW
-20%/+20% -35%/+50%
400 mW 2.0 W
http://onsemi.com
24
NCN6004A
NOTE:
Operating conditions under full output load.
Figure 17. Typical CRD_VCC Ripple Voltage
Figure 18. Typical Card Voltage Turn ON and Start-up Sequence
Figure 19. Typical Card Supply Turn OFF
74 Vout = 3.0 V 72 Vout = 5.0 V 70 68 Eff (%) 66 Vout = 1.8 V 64 62 60 58 2.5 3.0 3.5 4.0 Vbat (V) 4.5 5.0 5.5 Lout = 22 mH ESR = 2 W
The curves in Figure 20, illustrate the typical behavior under full output current load (35 mA, 60 mA and 65 mA), according to EMV specifications. During the operation, the inductor is subject to high peak current as depicted in Figure 21 and the magnetic core must sustain this level of current without damage. In particular, the ferrite material shall not be saturated to avoid uncontrolled current spike during the charge up cycle. Moreover, since the DC/DC efficiency depends upon the losses developed into the active and passive components, selecting a low ESR inductor is preferred to reduce these losses to a minimum.
Figure 20. CRD_VCC Efficiency as a Function of the Input Supply Voltage http://onsemi.com
25
NCN6004A
Test conditions: Input VCC voltage = 5.0 V, Current = 200 mA /div, Tamb = +20C
Figure 21. Typical Output Voltage Ripple
According to the ISO7816-3 and EMV specifications, the interface shall limits the CRD_VCC output current to 200 mA maximum, under short circuit conditions. The
180 160 140 120 Iout (mA) 100 80 60 40 Vo = 3.0 V Vo = 5.0 V
NCN6004A supports such a parameter, the limit being depending upon the input and output voltages as depicted in Figure 22.
160 150 140 Iout (mA) Vo = 5.0 V
Vo = 1.8 V
130 120 110
Vo = 3.0 V Vo = 1.8 V
20 0 2 3
IO(max) = F(Vbat) 4 Vbat (V) 5 6 100 -25 -5.0 15 35 55 75 TEMPERATURE (C) 95 115
Figure 22. Output Current Limit
Figure 23. Output Current Limit as a Function of the Temperature
Beside the continuous current capability, the smart card power supply must be capable of providing a 100 mA pulsed current during the data transaction. The ISO7816-3, paragraph 4.3.2, defines this 400 ns pulse as a function of the
environment. As a matter of fact, this pulse does not come solely from the NCN6004A DC/DC converter, but the reservoir capacitor and the associated PCB tracks shall be considered as well.
http://onsemi.com
26
NCN6004A
CLOCK DIVIDER The main purpose of the built in clock generator is four folds: 1. Adapts the voltage level shifter to cope with the different voltages that might exist between the MPU and the Smart Card 2. Provides a frequency division to adapt the Smart Card operating frequency from the external clock source. 3. Control the clock state according to the smart card specification. 4. Provides an input clock re-routing to route the CLOCK_IN_A and CLOCK_IN_B signals to either CRD_CLK_A or CRD_CLK_B output pins.
CLOCK_IN_A CLOCK_IN_B CS 1 3 2 PGM A2 A2 A1 A0 CARD_SEL CARD_A CLOCK_AB DIVIDER MUX_A&B CLOCK_A DIVIDER LOGIC CONTROL CRD_VCC_A
In addition, the NCN6004A adjusts the signal coming from the microprocessor to get the Duty Cycle window as defined by the ISO7816-3 specification. The logic input pins CARD_SEL, A0, A1, PGM, I/O and RESET fulfill the programming functions when both PGM and CS are Low. The clock input stage (CLOCK_IN) can handle a 40 MHz frequency maximum, the divider being capable to provide an 1:8 ratio. Of course, the ratio must be defined by the engineer to cope with the Smart Card considered in a given application and, in any case, the output clock (CRD_CLK_A and CRD_CLK_B) shall be limited to 20 MHz maximum when the system is considered to operate over the full temperature range.
LEVEL SHIFTER & CONTROL
CRD_CLK_A
CRD_VCC_B
CARD_B
MUX_A&B
LEVEL SHIFTER & CONTROL
CRD_CLK_B
DC/DC BLOCK_A
CRD_VCC_A
DC/DC BLOCK_B
CRD_VCC_B
CARD_A & CARD_B CLOCK
Figure 24. Simplified Frequency Divider and Programming Functions
In order to avoid any duty cycle out of the frequency smart card ISO7816-3 and EMV specifications, the clock divider is synchronized by the last flip flop, thus yielding a constant 50% duty cycle, regardless of the divider ratio.
Consequently, the output CRD_CLK_A or CRD_CLK_B frequency division can be delayed by eight CLOCK_IN pulses and the microcontroller software must take this delay into account prior to launch a new data transaction.
http://onsemi.com
27
NCN6004A
CLOCK_IN CLOCK : 2 CLOCK : 4 CLOCK : 8 CS PGM CLOCK = 1:1 ratio These bits program Clock is updated upon CLOCK :8 rising edge CARD_SEL A0 A1 A2 A3 Internal CLOCK divider
CRD_CLK CLOCK programming is activated by the PGM rising edge.
Figure 25. Clock Programming Timings
The example given in Figure 25 highlights the delay coming from the internal clock duty cycle re-synchronization. Since the clock signal is asynchronous, it is up to the programmer to make sure the next card transaction is not activated before, respectively, either the
CRD_CLK_A or CRD_CLK_B signal has been updated. Generally speaking, such a delay can be derived from the maximum clock frequency provided to the interface.
Figure 26. Card Clock 1/2 Divider Operation
http://onsemi.com
28
NCN6004A
Figure 27. Clock Divider: 8 to 1 Operation
Figure 28. Clock Divider Timing Details
Figure 29. Clock Divider: Run to Stop High Operation
http://onsemi.com
29
NCN6004A
The input clock A and B can be re routed to either CRD_CLK_A or CRD_CLK_B output pins by using the programming function as defined in Table 2 and Table 7. The clock signals can have any frequency value necessary to handle a given type of card (asynchronous or synchronous).
Table 7. Programming Clock Routing
STATE 0E 0F 0E 0F CS 0 0 0 0 PGM 0 0 0 0 A3 1 1 1 1 A2 1 1 1 1 A1 1 1 1 1 A0 0 1 0 1 CARD_SEL 1 1 0 0 CRD_CLK_A CLK_D_A CLK_D_B - - CRD_CLK_B - - CLK_D_B CLK_D_A Default - Default -
These clock signals can be multiplexed at any time, but the system must be locked in a safe state prior to make such a change. In particular, the designer must make sure that A and B cards can support such a hot change prior to change the related clocks.
On the other hand, the slope of the CRD_CLK_x signal can be set to either FAST or SLOW, depending upon the
Table 8. Output Clock Slope Selection
STATE $03 $0B $03 $0B CS 0 0 0 0 PGM 0 0 0 0 A3 0 1 0 1 A2 0 0 0 0 A1 1 1 1 1 A0 1 1 1 1
frequency of the output clock. This selection is achieved by programming the chip according to Table 8.
CARD_SEL 1 1 0 0
CLOCK SLOPE SLOW FAST SLOW FAST Default - Default -
Figure 30. Typical Rise and Fall Time in Fast and Slow Operating Mode
PARALLEL OPERATION When two or more NCN6004A parts operate in parallel on a common digital bus, the Chip Select pin allows the selection of one chip from the bank of the paralleled devices. Of course, the external MPU shall provide one unique CS line for each of the NCN6004A considered interface. When a given interface is selected by CS = L, all the logic inputs becomes active, the chip can be programmed or/and the external card can be accessed. When CS = H, all the input logic pins are in the high impedance state, thus leaving the bus available for other purpose. The pull up resistors connected on each logic input lines on the MPU side (see block diagram in Figure 30), can be either activated (connected to VCC) or disconnected, depending upon the logic state present at EN_RPU, pin 45. When these resistors are disconnected, it is the system responsibility to set up the external pull up resistors according to the application's requirements. When the device operates in the multiplexed mode (MUX_MODE = High), the internal card #B pull up resistors are connected to VCC, regardless of the EN_RPU logic state. On the other hand, when CS = H, the CRD_IO and CRD_RST hold the previous I/O and RESET logic state, the CRD_CLK being either active or stopped and the CRD_VCC output voltage will maintain is previous value, according to the programmed state forced by the MPU.
http://onsemi.com
30
NCN6004A
CLOCK GEN. CLOCK GEN. PORT A CLK_IN_A CLK_IN_B RESET_A C4_A C8_A I/O_A I/O_B C8_B C4_B RESET_B GND MUX_MODE CTL CARD_SEL 13 MULTIPLEX & CLOCK DIVIDER 15 10 11 12 9 19 16 17 18 44 5 CARD LOGIC CONTROL CLK_A BUFFER CLK_B BUFFER 30 31
MICRO CONTROLLER
BUFFERS CARD_A I/O_A BUFFER I/O_B BUFFER CARD_B BUFFERS
23 22 21 24 37 38 39 40
Figure 31. Parallel Operation Wiring " MUX_MODE = Low
When the chip operates in the parallel mode, all the logic signals must be independently controlled by the microcontroller as depicted in Figure 31. The MUX_MODE pin must be hardwired to VCC and it cannot be changed
CLOCK GEN. CLOCK GEN. PORT A CLK_IN_A CLK_IN_B RESET_A C4_A C8_A I/O_A I/O_B C8_B C4_B RESET_B VCC MUX_MODE CARD_SEL 13
PORT B
during an operation of the chip. Beside this parameter, the user must select to force or not the internal pull up resistors as defined by the EN_RPU logic state.
MULTIPLEX & CLOCK DIVIDER 15 10 11 12 9 19 16 17 18 44 5 CARD LOGIC CONTROL
CLK_A BUFFER CLK_B BUFFER
30 31
MICRO CONTROLLER
BUFFERS CARD_A I/O_A BUFFER I/O_B BUFFER CARD_B BUFFERS
23 22 21 24 37 38 39 40
Figure 32. Multiplexed Operation Wiring " MUX_MODE = High
In the multiplexed mode, the microprocessor CARD_B side pins are not connected, the logic signals and the I/O line being shared with CARD_A associated with the CRD_SEL control bit: Figure 32. A key point is to make sure there is no connection associated with the I/O_B pin since this pin is internally shared with the I/O line transaction. The CLK_IN_A and CLK_IN_B signals are independent and can be routed to any of the card thanks to the built-in clock multiplexer. DATA I/O LEVEL SHIFTER The built in structure provides a level shifter on each card output signals, the I/O line being driven differently as depicted in Figure 33. Since the NCN6004A can operate in
CTL
PORT B
either a multiplexed or parallel mode, provisions have been made to route the I/O_A input pin to either CARD_A or CARD_B. In both case, the I/O pins are driven by an open drain structure with a 20 kW pull up resistor as shown Figure 33. To achieve the 0.80 ms maximum rise time requested by the EMV specifications, an accelerator circuit is added on both side of each I/O line. These pulsed circuits yield boost current to charge the stray capacitance, thus accelerating the positive going slope of the I/O signal. On the other hand, the active pull down NMOS device Q5 provides a low impedance to ground during the battery up and DC/DC start-up phase, avoiding any uncontrolled voltage spikes on the I/O lines.
http://onsemi.com
31
NCN6004A
MUX_MODE = Low " PARALLEL OPERATION
The bi-directional switch Q9 is OFF and the I/O signals are routed straightforward to their appropriate outputs. The two I/O lines can operate simultaneously, depending upon the mP capabilities, regardless of the CARD_SEL signal logic level. The pull up resistors, on the mP side of each I/O line, can be connected or not as defined by the EN_RPU signal.
MUX_MODE = High " MULTIPLEXED OPERATION
The bi-directional switch Q9 is ON and the I/O_A pin is used to handle data for CARD_A and CARD_B. The signal
ANLG_VCC MUX_MODE 42 Q10 44
is routed to the appropriate card by means of the CARD_SEL logic signal. In this mode, the I/O_B pin 19 must be left open since the internal data signal will be present on this pin. Moreover, since R1 and R3 are in parallel, the pull up resistor R1 is automatically disconnected to maintain the I/O line impedance to 20 kW (typical), what ever be the EN_RPU logic level. This feature makes sure the current flowing trough the external card is limited to 500 mA during a low level state.
29 Q1 R1 I/O_A 9 BI-DIRECTIONNAL DATA TRANSFERT Q2 R2 24
CRD_VCC_A
Q3 CONTROL LOGIC & Level Shifter
Q4
CRD_I/O_A
Q5 CRD_VCC_A Q11 ANLG_VCC GND
32 Q9 R3 Q6 BI-DIRECTIONNAL DATA TRANSFERT Q11 R4
CRD_VCC_B
I/O_B PGM PWR_ON CS CARD_SEL EN_RPU
19 6 8 7 5 45 CONTROL LOGIC & Level Shifter
Q7
Q8
37
CRD_I/O_B
Q10 CRD_VCC_B ANLG_VCC GND
Figure 33. Dual Bi-directional I/O Line Level Shifter and Multiplex
http://onsemi.com
32
NCN6004A
NOTE:
Both sides of the interface run with open drain load (worst case condition)
Figure 34. Typical I/O Rise and Fall Time
ESD Protection The NCN6004A includes silicon devices to protect the pins against the ESD spikes voltages. To cope with the different ESD voltages developed across these pins, the built in structures have been designed to handle either 2 kV, when related to the microcontroller side, or 8 kV when connected with the external contacts. Practically, the CRD_RST, CRD_CLK, CRD_IO, CRD_C4 and CRD_C8 (both A and B sections) pins can sustain 8 kV, the maximum short circuit current being limited to 15 mA. The CRD_VCC_A and CRD_VCC_B pins have the same ESD protection, but can source up to 65 mA continuously each, the absolute maximum current being 150 mA per section. Security Features In order to protect both the interface and the external smart card, the NCN6004A provides security features to prevent catastrophic failures as depicted here after. Pin Current Limitation: in case of a short circuit to ground, the current forced by the device is limited to 10 mA for any pins, except CRD_CLK_A and CRD_CLK_B pins
which are both limited to 70 mA. No feedback is provided to the external MPU. DC/DC Operation: The internal circuit continuously senses the CRD_VCC_A and CRD_VCC_B voltages and, in the case of either over or under voltage situation, update the STATUS register accordingly. This register can be read out by the MPU but no interrupts are activated. DC/DC Overload: When an overload is sensed across the CRD_VCC_A or CRD_VCC_B output, during either the power on sequence or when the system was previously running, the NCN6004A generates an interrupt by pulling down the INT pin. It is up to the microcontroller to identify the origin of the overload by reading the STATUS pin accordingly. Battery Voltage: Both the Positive going and the Negative going voltage are detected by the NCN6004A, a POWER_DOWN sequence and the STATUS register being updated accordingly. The external MPU can read the STATUS pin to take whatever is appropriate to cope with the situation. The NCN6004A does not provide any further internal voltage regulation.
http://onsemi.com
33
NCN6004A
TEST BOARD SCHEMATIC DIAGRAM
220 nF C6 + GND GND VCC_A GND C9 0R C7 + GND R17 GND J2 6 I/O 7 VPP GND 5 Vcc 1 RST 2 CLK 3 C4 4 C8 8 Swb 9 Swa 10 SMARTCARD_B ISO7816 GND 4.7 mF, X7R C10 C13 VCC D6 R12 2N2222 GND Q2 R15 10 k IO_A GND 220 nF C14
CRD_VCC_A 1.5 k C12 4.7 mF, X7R GND J12 7 I/O VPP 6 5 GND 1 Vcc 2 RST 3 CLK 4 8 C4 9 C8 10 Swb Swa SMARTCARD_A 1 1 CARD_A_INS RST_A CLK_A 10 mF C8 1 1 1 1 Det_A TP12 IO_A TP11 C8_A TP10 C4_A TP9 TP8 CLK_A TP7 RST_A U1 ISO7816 1 CLK_B J8 1 CLK_IN_A CLK_IN_B 1 J6 2 1 2 EXT_CLK MPU_CLK GND 100 nF VCC C1 GND 100 nF C2
C_CLK_B VCC_B
GND
TP5 IO_B
1 TP4 C8_B 1
2 J10
TP3 C4_B
1 1 TP2 CLK_B TP6 RST_B R14 10 k 1 2 R16 1 J9 CRD_VCC_B C5 +
4.7uF, X7R 1 R13 CRD_VCC_A
1.5 k D5 C3 VCC + 10 mF, X7R 0R
Q1
2N2222
IO_B
24 CRD_IO_A 21 CRD_C8_A 22 CRD_C4_A 30 CRD_CLK_A 23 CRD_RST_A 29 CRD_VCC_A 20 CRD_DET_A GND 25 PWR_GND 36 PWR_GND
GND TP1 1 Det_B
GND
4.7 mF, X7R
28 PWR_VCC_A 33 PWR_VCC_B 37 CRD_IO_B 40 CRD_C8_B 39 CRD_C4_B 31 CRD_CLK_B 38 CRD_RST_B 32 CRD_VCC_B 41 CRD_DET_B
R11 1.5 k
R10 1.5 k L2
35 L2b
22 mH
34 26 L1b L1a
D4 CRD_VCC_B VCC GND 1 S1 4 3 2 SWITCH R2 4.7 k
D3 CRD_B_INS R3 9 8 7 6 5 4 3 2 1 8x10k VCC
NCN6004 C4_A RESET_A I/O_A INT STATUS EN_RPU MUX_MODE PWR_ON CS PGM CARD_SEL A3 A2 A1 A0 ANLG_GND CLK_IN_A CLK_IN_B RESET_B C4_B C8_B
L1
22 mH
27 L2a
VCC
GND
MUX_MODE EN_RPU
TP24 1 INT R1 TP23 1 4.7 k Status VCC TP22 1 PWR_ON TP20 1 A0 TP21 1 A1 TP19 1 A2 TP18 A3 TP17 1 Card_Sel TP16 1 PGM TP15 1 CS VCC J1
J4 2 CLK_A 1 J3 1 J7 2 1 D2 C8_A RESET_A C4_A E STATUS
2 GROUND GROUND GROUND GND EXT_CLK J14 1 2 J13 1 2 J11 1 2 C8_B C4_B RESET_B
TP13 I/O_A PWR_ON CS PGM CARD_SEL
1
VCC LED LED INT I/O_A D1
R5 R4 1.5k 1.5k
J5 2 MPU_CLK I/O_B
CONTROL & I/O
Figure 35. Test Board Schematic Diagram
http://onsemi.com
34
+ CLK_IN
48 ANLG_GND 43 ANLG_GND C11 ANLG_VCC 42
GND 100 nF, X7R
C8_A
I/O_B
11 10 9
12
13
19 18 17 16 15
14
47 46 45 44 8 7 6 5 4 3 2 1 STATUS A3 A2 A1 A0
I/O_B TP14
GND 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
NCN6004A
Figure 36. Demo Board PCB Top Overlay
http://onsemi.com
35
NCN6004A
Figure 37. Demo Board PCB Top Layer
http://onsemi.com
36
NCN6004A
Figure 38. Demo Board PCB Bottom Layer
NOTE: Note: the demo board is built with a four layers PCB, the internal ones being dedicated to VCC and GND planes.
http://onsemi.com
37
NCN6004A
PIN FUNCTIONS AND DESCRIPTION . . . . . . 4 POWER SUPPLY SECTION . . . . . . . . . . . . . . . 10 DIGITAL INPUT SECTION @ 2.70 < VCC < 5.50V, Normal Operating Mode . . . . . . . . . . . . . . . . . . 11 CARD INTERFACE SECTION @ 2.70 < VCC < 5.50V, Normal Operating Mode . . . . . . . . . . . . . . . . . . 12 DIGITAL DYNAMIC SECTION NORMAL OPERATING MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 DIGITAL DYNAMIC SECTION PROGRAMMING MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 PROGRAMMING AND STATUS FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 SYSTEM STATES UPON START UP . . . . . . . 16 PARALLEL/MULTIPLEXED OPERATION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 CARD POWER SUPPLY TIMING . . . . . . . . . . . 18 POWER DOWN OPERATION . . . . . . . . . . . . . . 18 CARD DETECTION . . . . . . . . . . . . . . . . . . . . . . 20 POWER MANAGEMENT . . . . . . . . . . . . . . . . . . 21 OUTPUT VOLTAGE PROGRAMMING . . . . . . 21 DC/DC CONVERTER . . . . . . . . . . . . . . . . . . . . . 22 CLOCK DIVIDER . . . . . . . . . . . . . . . . . . . . . . . . 27 PARALLEL OPERATION . . . . . . . . . . . . . . . . . . 30 DATA I/O LEVEL SHIFTER . . . . . . . . . . . . . . . . 31 ESD PROTECTION . . . . . . . . . . . . . . . . . . . . . . 33 SECURITY FEATURES . . . . . . . . . . . . . . . . . . . 33 TEST BOARD SCHEMATIC DIAGRAM . . . . . 34 Figures Figure 1: Pin Diagram . . . . . . . . . . . . . . . . . . . . 2 Figure 2: Typical Applications . . . . . . . . . . . . 2 Figure 3: Block Diagram . . . . . . . . . . . . . . . . . 3 Figure 4: Programming Sequence . . . . . . . . 14 Figure 5: Reading ANLG_VCC Status . . . . . 16 Figure 6: Simplified MUX_MODE Logic and Multiplex CIrcuit . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 7: Card Power Supply Turn ON and Shut OFF Typical Sequence . . . . . . . . . . . . . . 18 Figure 8: Card Power Down Sequence . . . . 18 Figure 9: Power Down Sequence . . . . . . . . . 19 Figure 10: Power Down Sequence: Timing Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 11: Typical Interrupt Sequence . . . . . 20 Figure 12: Card Power Supply Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 13: Power On Sequence Timing . . . . 22 Figure 14: Power On and CARD_SEL Sequence Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 15: Basic DC/DC Converter Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 16: Theoretical DC/DC Operating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 17: Typical CRD_VCC Ripple Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 18: Typical Card Voltage Turn ON and Start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 19: Typical Card Supply Turn OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 20: CRD_VCC Efficiency as a Function of the Input Supply Voltage . . . . . . . . . . . . . . . . . . . . 25 Figure 21: Typical Output Voltage Ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 22: Output Current Limit . . . . . . . . . . . 26 Figure 23: Output Current Limit as a Function of the Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 24: Simplified Frequency Divider and Programming Functions . . . . . . . . . . . . . . . . . 27 Figure 25: Clock Programming Timings . . . 28 Figure 26: Card Clock 1/2 Divider Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 27: Clock Divider: 8 to 1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 28: Clock Divider Timing Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 29: Clock Divider: Run to Stop High Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 29: Typical Rise and Fall Time in Fast and Slow Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 30: Parallel Operation Wiring " MUX_MODE = High . . . . . . . . . . . . . . . . . . . . . . 30 Figure 31: Multiplexed Operation Wiring " MUX_MODE = Low . . . . . . . . . . . . . . . . . . . . . . 31 Figure 32: Dual Bi-directional I/O line Level Shifter and Multiplex . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 33: Typical I/O Rise and Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 34: Test Board Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 35: Demo Board PCB Top Overlay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 37: Demo Board PCB Top Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 38: Demo Board PCB Bottom Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 1 :Programming and Reading Basic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 2: Programming Functions . . . . . . . . . 15 Table 3: Status Pins Data . . . . . . . . . . . . . . . . 16 Table 4: Operating Conditions Upon Start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 5: Card Detection Polarity . . . . . . . . . . 20 Table 6: Ceramic/Electrolytic Capacitors Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 7: Programming Clock Routing . . . . . 30 Table 8: Output Clock Slope Selection . . . . 30
http://onsemi.com
38
NCN6004A
ABBREVIATIONS
L1a and L1b L2a and L2b Cout CRD_VCC VCC Icc Class A CS CRD_CLK_B CRD_IO_B CRD_IO_B EMV Class B ANLG_VCC = VCC = Vbat PWR_ON MUX_MODE CRD_DET_B T1 DC/DC external inductor #A DC/DC external inductor #B Output Capacitor Card Power Supply Input MPU Power Supply Voltage Current at card VCC pin 5 V Smart Card Chip Select Interface IC Card #B Clock Input Interface IC Card #B Data link Interface IC Card #B RESET Input Euro Card Master Card Visa 3 V Smart Card Input Voltage Chip Power On bit Card Multiplex or Parallel Op. Card insertion/extraction detection Smart Card Data transfer procedure by strings T0 mC Smart Card Data transfer procedure by bytes Microcontroller EN_RPU PGM ISO CRD_VCC_B CRD_C4_B CRD_C8_A Enable/Disable internal pull up Chip Programming Mode International Standards Organization Interface IC Card #B Power Supply Line Interface IC Card #B Data Control Interface IC Card #B Data Control CRD_VCC_A CRD_CLK_A CRD_RST_A CRD_IO_A CRD_C4_A CRD_C8_A CRD_DET_A CARD_SEL Interface IC Card #A Power Supply Line Interface IC Card #A Clock Input Interface IC Card #A RESET Input Interface IC Card #A Data link Interface IC Card #A Data Control Interface IC Card #A Data Control Card insertion/extraction detection Card #A/B Selection bit
http://onsemi.com
39
NCN6004A
PACKAGE DIMENSIONS
48 LEADS, TQFP EP CASE 932F-01 ISSUE A
4 PL NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE AB IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS T, U, AND Z TO BE DETERMINED AT DATUM PLANE AB. 5. DIMENSIONS S AND AB TO BE DETERMINED AT SEATING PLANE AC. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE AB. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.350. 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076. 9. EXACT SHAPE OF EACH CORNER IS OPTIONAL. MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 0.900 1.100 0.170 0.270 0.950 1.250 0.170 0.230 0.500 BSC 0.050 0.150 0.090 0.200 0.500 0.700 0_ 7_ 12_ REF 0.090 0.160 0.250 BSC 0.150 0.250 9.000 BSC 4.500 BSC 5.000 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF
0.200
M
AB T-U Z DETAIL Y
37
A T
NOTE 9 48
A1
1
36
T B B1
12 25
U V V1
P
AE
AE
13
24
Z S1 S 0.200
4 PL M
EXPOSED PAD
T, U, Z DETAIL Y
AC T-U Z
AB
G 0.080 AC AD
NJ
F D
AC M
SEATING PLANE
0.080
M
AC T-U Z
SECTION AE-AE R
TOP & BOT
DIM A A1 B B1 C D E F G H J K L M N P R S S1 T V V1 W AA
CE W
0.250 L
GAUGE PLANE
H
K AA DETAIL AD
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: N. American Technical Support: 800-282-9855 Toll Free Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 61312, Phoenix, Arizona 85082-1312 USA Phone: 480-829-7710 or 800-344-3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Fax: 480-829-7709 or 800-344-3867 Toll Free USA/Canada Phone: 81-3-5773-3850 Email: orderlit@onsemi.com ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative.
http://onsemi.com
40
ECEE E ECCC EEC ECCE ECC EE
NCN6004A/D

▲Up To Search▲

Price & Availability of NCN6004A06

	To Download NCN6004A06 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .